Digital Electronic Circuits Assignment Help - Level 5 HND Electrical & Electronic Engineering

TASK1:

a) Nominal values of logic families:

EXAMPLE:

LSTTL: MC74HCT08A: Quad 2-input AND Gate with LSTTL Compatible Inputs:

ALSTTL: SN54ALS04B: HEX INVERTER

CMOS: CD4027BMS: CMOS Dual J-K Master - Slave Flip - Flop:

HCMOS: 74HC/HCT/HCU family;

b)     Fan-Out:

The number of digital Input that can feed by any single logic gate for the output.

For Example: TTL gates can feed up to 10 inputs from other digital gates or devices. This means TTL gate has fan-out = 10.

Noise Margin:

Noise margin is the amount of noise that a CMOS circuit could withstand without compromising the operation of circuit. It does make sure that, any signal which is logic '1' with finite noise added to it, is still recognized as logic '1' and not logic '0'. It is basically the difference between signal value and the noise value.

Ideally, when input voltage is logic '1', output voltage is supposed to be at logic '0'. Hence, Vih (V input high) is 'Vdd', and Vol (V output low) is '0'V.
Vih = Vdd 
Vol = 0 

Noise Margins could be defined as follows : 
NMl (NOISE MARGIN low) = Vil - Vol = 0 - 0 = 0 
NMh (NOISE MARGIN high) = Voh - Vih = Vdd - Vdd = 0 

REFERENCES:

1) Texas Instruments Datasheet.

2) Intersil Datasheet.

3) Alldatasheet. Com.

4) Philips Semiconductors.

TASK2:

a)      Boolean Expression:

OUTPUT, Y= AB'(C      D) = AB'C'D + AB'CD'

b)     Boolean Expression in SOP form:

OUTPUT, Y= AB'C'D + AB'CD'

c)      Simulation : (Opportunity of Distinction)

Circuit Diagram:

FINAL OUTPUT:

OUTPUT FOR EACH BIT:

 OUTPUT FROM LOGIC ANALYSER:

 d)     Truth Table:

K-MAP (Opportunity of Merit)

                CD   00                                01                                11                                10

Boolean Expression:

OUTPUT, Y= AB'C'D + AB'CD'

e)      CIRCUIT OPERATION: (Opportunity of Distinction)

According to the output expression generated two 4-input AND gates are connected to generate AB'C'D and  AB'CD'.

After that for sum of these two OR gate is used and form a combination of AB'C'D + AB'CD'.

Finally output is shown by logic analyzer, where each inputs and output are shown in one figure but in different line.

In CRO all inputs and output are shown in same line.

REFERENCES:

1)      Digital Circuits and Design by S. Salivahanan and S Arivazhagan.

2)      Digital Circuit design by Tocci.

TASK 3:

a)      Design a 4-bit asynchronous counter using JK flip -flop to count between 2 and 9:

Flow Diagram:

To design a counter with 8 states, the number of flip-flops required can be found using the equation 2^n>=N >=2^n-1

Where n = number of flip flop required.

N = Number of states present in the counter.

For given condition N = 8 Number of states present in the counter

Thus n = 3 number of flip flop required.

Sequence Table:

Excitation Table:

Karnaugh Map for J₀ :

             q₁q₀    00                                01                                11                                10

Boolean Expression:

OUTPUT, J₀= q₃'q₁q₀' + q₃' q₂q₀' + q₃q₂'q₁'q₀'

Karnaugh Map for K₀ :

             q₁q₀            00                                           01                                           11                                           10

Boolean Expression:

OUTPUT, J₀= q₃'q₁q₀ + q₃' q₂ + q₃q₂'q₁'q₀

b)     Simulation: (Opportunity of Distinction)

Output

OUTPUT TRUTH TABLE: (Opportunity of Merit)

CIRCUIT OPERATION FOR ASYNCHRONOUS UP COUNTER TO COUNT 0 TO F

Above circuit shows the asynchronous counter to count from 2 to 9. According to requirement initial value is set to 2 and then starts counting. Here it is up counting from 2 to 9. MSB and LSB are connected to a NAND gate. If both inputs are high then based on NAND truth table OUTPUT of NAND gate is LOW.  When 9 comes means MSB and LSB are HIGH then NAND gives OUTPUT LOW. As this OUTPUT terminal is connected to clear line of 3 FFs except C bit, all are these 3 are cleared and bit C is connected via NOT gate to the SET of this FF. As a result OUTPUT generated is 0010. Then start again and again.

REFERENCES:

1)      Digital Circuit design by Tocci.

2)      Digital Circuits and Design by S. Salivahanan and S Arivazhagan.

PART  A:

a)      Boolean Expression:

OUTPUT, Y= AB'(C      D) = AB'(C EXOR  D)  =AB'C'D + AB'CD'

b)     Boolean Expression in SOP form:

OUTPUT, Y= AB'C'D + AB'CD'

c)      Simulation : (Opportunity of Distinction)

Circuit Diagram:

 Output for AB'CD'

Output for AB'C'D

OUTPUT FINAL ONLY:

OUTPUT FOR EACH BIT:

OUTPUT FROM LOGIC ANALYSER:

d)     Truth Table:

K-MAP (Opportunity of Merit)

                CD   00                                01                                11                                10

Boolean Expression:

OUTPUT, Y= AB'C'D + AB'CD'

e)  CIRCUIT OPERATION: (Opportunity of Distinction)

According to the output expression generated two 4-input AND gates are connected to generate AB'C'D and  AB'CD'.

After that for sum of these two OR gate is used and form a combination of AB'C'D + AB'CD'.

Finally output is shown by logic analyzer, where each inputs and output are shown in one figure but in different line.

In CRO all inputs and output are shown in same line.

REFERENCES:

1) Digital Circuits and Design by S. Salivahanan and S Arivazhagan.

2) Digital Circuit design by Tocci.

PART B:

a) Design a 4-bit asynchronous counter using JK flip -flop to count between 2 and 9:

Flow Diagram:

To design a counter with 8 states, the number of flip-flops required can be found using the equation 2^n>=N >=2^n-1

Where n = number of flip flop required.

N = Number of states present in the counter.

For given condition N = 8 Number of states present in the counter

Thus n = 3 number of flip flop required.

Sequence Table:

Excitation Table:

Karnaugh Map for J₀ :

             q₁q₀    00                                01                                11                                10

 Boolean Expression:

OUTPUT, J₀= q₃'q₁q₀' + q₃' q₂q₀' + q₃q₂'q₁'q₀'

Karnaugh Map for K₀ :

             q₁q₀            00                                           01                                           11                                           10

Boolean Expression:

OUTPUT, K₀= q₃'q₁q₀ + q₃' q₂ + q₃q₂'q₁'q₀

b)     Simulation: (Opportunity of Distinction)

Step 1: Design basic asynchronous UP counter to count 0 to F

Output:

Step2: Then design for upto 9

Place a NAND gate having 2 inputs. When combination "9" comes it generates Zero output.

Step 3: then connect to that output to clear line. That means it will clear output when 9 comes and start from initial value.

Step 4: Use a NOT gate to generate high signal to set D1 bit high for initial value "2"

OUTPUT TRUTH TABLE: (Opportunity of Merit)

CIRCUIT OPERATION FOR ASYNCHRONOUS UP COUNTER TO COUNT 0 TO F

Above circuit shows the asynchronous counter to count from 2 to 9. According to requirement initial value is set to 2 and then starts counting. Here it is up counting from 2 to 9. MSB and LSB are connected to a NAND gate. If both inputs are high then based on NAND truth table OUTPUT of NAND gate is LOW.  When 9 comes means MSB and LSB are HIGH then NAND gives OUTPUT LOW. As this OUTPUT terminal is connected to clear line of 3 FFs except C bit, all are these 3 are cleared and bit C is connected via NOT gate to the SET of this FF. As a result OUTPUT generated is 0010. Then start again and again.

REFERENCES:

1)      Digital Circuit design by Tocci.

2)      Digital Circuits and Design by S. Salivahanan and S Arivazhagan.