Programme: HND Electrical & Electronic Engineering

Unit Number and Name: Unit 66 Electrical, Electronic and Digital Principles T/601/1395

Level: QCF Level 5

Assignment Title - Digital Electronic Circuits

You have completed your engineering apprenticeship and have a position in the design department of your company. You have been asked by your line manager, Mithun, to produce a combinational logic circuit (Task 2). For Task 3 you have been requested to evaluate the operation of JK Flip Flops and present your findings and measurements to your line manager.

a) Using Manufacturer's datasheets complete the table below using Nominal values for the logic families.

 LS TTL ALS TTL CMOS HCMOS VIL VIH AIL IIH VOL VOH COL LOH Fan-out Noise Margin

b) Define the terms Fan-out and Noise Margin.

Design a circuit whose output goes HIGH when its inputs are. A is high and B is low and either input C or input D is also HIGH

Procedure:
a) Derive a Boolean that describes the performance of the required circuit.
b) Rearrange the expression in Sum-of-Products (SOP) form.
c) Using simulation software, Draw the circuit diagram and simulate its operation.
d) Produce a four-variable truth table and apply all combinations of input variables to the circuit and each time note the logical state.
e) Demonstrate the circuit operation to your tutor.

 A B C D F 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1

Opportunity for Distinction (Part A) (Both Part A and Part B must be completed for D2) Demonstrate, with photographic evidence, that you have simulated the circuit in Task 2 without any help from your peers and/or tutor. D2

Opportunity for Merit

Use Karnaugh Maps to check the SOP found in Part b, is equivalent to the original Boolean expression. found in Part a. M2

a) Design a 4 bit asynchronous counter using JK flip flops to count between 2 and 9.
- Flow diagram
- Sequence table
- Karnaugh maps

b) Using a Logic Tutor or Multisim, construct the counter and demonstrate to your Tutor.

Opportunity for Merit

Produce a report containing the information found for TASKs 2 and 3. You will need to use a variety of word processing features and circuit diagrams created in Multisim. You will also need to use engineering language correctly. M3 Opportunity for Distinction (Part B) (Both Part A and Part B must be completed for D2) Demonstrate, with photographic evidence, that you have built the circuit in Task 3 without any help from your peers and/or tutor.

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a) Nominal values of logic families:

 LS TTL ALS TTL CMOS HCMOS VIL -0.5 V -1.2V 4V 0.8V VIH + 0.5 V -1.2V 11V 1.5V IIL -20 mA -0.1mA -100nA 0.1 uA IIH +20 mA 20uA 100nA 0.1 uA VOL -0.5 V 0.25V 50mV 0.1 V VOH + 0.5 V Vcc - 2 14.95mV 2.0 V IOL -20 mA -30mA 3.5mA 0.1 uA LOH +20 mA -112mA -3.5mA 0.1 uA Fan- out 10 >10 >10 >10 Noise Margin High High 1V at VDD = 5v High

EXAMPLE:

LSTTL: MC74HCT08A: Quad 2-input AND Gate with LSTTL Compatible Inputs:

ALSTTL: SN54ALS04B: HEX INVERTER

CMOS: CD4027BMS: CMOS Dual J-K Master - Slave Flip - Flop:

HCMOS: 74HC/HCT/HCU family;

b)     Fan-Out:

The number of digital Input that can feed by any single logic gate for the output.

For Example: TTL gates can feed up to 10 inputs from other digital gates or devices. This means TTL gate has fan-out = 10.

Noise Margin:

Noise margin is the amount of noise that a CMOS circuit could withstand without compromising the operation of circuit. It does make sure that, any signal which is logic '1' with finite noise added to it, is still recognized as logic '1' and not logic '0'. It is basically the difference between signal value and the noise value.

Ideally, when input voltage is logic '1', output voltage is supposed to be at logic '0'. Hence, Vih (V input high) is 'Vdd', and Vol (V output low) is '0'V.
Vih = Vdd
Vol = 0

Noise Margins could be defined as follows :
NMl (NOISE MARGIN low) = Vil - Vol = 0 - 0 = 0
NMh (NOISE MARGIN high) = Voh - Vih = Vdd - Vdd = 0

REFERENCES:

1) Texas Instruments Datasheet.

2) Intersil Datasheet.

3) Alldatasheet. Com.

4) Philips Semiconductors.

a)      Boolean Expression:

OUTPUT, Y= AB'(C      D) = AB'C'D + AB'CD'

b)     Boolean Expression in SOP form:

OUTPUT, Y= AB'C'D + AB'CD'

c)      Simulation : (Opportunity of Distinction)

Circuit Diagram:

FINAL OUTPUT:

OUTPUT FOR EACH BIT:

OUTPUT FROM LOGIC ANALYSER:

d)     Truth Table:

 INPUTS OUTPUT A B C D Y 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 1 0 0 0 1 1 1 0 1 0 0 0 0 1 0 0 1 1 1 0 1 0 1 1 0 1 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 0 0 1 1 1 1 0

K-MAP (Opportunity of Merit)

 AB 00 01 11 10

CD   00                                01                                11                                10

 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

Boolean Expression:

OUTPUT, Y= AB'C'D + AB'CD'

e)      CIRCUIT OPERATION: (Opportunity of Distinction)

According to the output expression generated two 4-input AND gates are connected to generate AB'C'D and  AB'CD'.

After that for sum of these two OR gate is used and form a combination of AB'C'D + AB'CD'.

Finally output is shown by logic analyzer, where each inputs and output are shown in one figure but in different line.

In CRO all inputs and output are shown in same line.

REFERENCES:

1)      Digital Circuits and Design by S. Salivahanan and S Arivazhagan.

2)      Digital Circuit design by Tocci.

a)      Design a 4-bit asynchronous counter using JK flip -flop to count between 2 and 9:

Flow Diagram:

To design a counter with 8 states, the number of flip-flops required can be found using the equation 2^n>=N >=2^n-1

Where n = number of flip flop required.

N = Number of states present in the counter.

For given condition N = 8 Number of states present in the counter

Thus n = 3 number of flip flop required.

Sequence Table:

 PRESENT STATE (PS) NEXT STATE (NS) q3q2q1q0 Q3Q2Q1Q0 0010 0011 0011 0100 0100 0101 0101 0110 0110 0111 0111 1000 1000 1001 1001 0010

Excitation Table:

 PRESENT STATE (PS) NEXT STATE (NS) Excitation Inputs q3q2q1q0 Q3Q2Q1Q0 J3 K3 J2 K2 J1 K1 J0 K0 0010 0011 0 d 0 d d 0 1 d 0011 0100 0 d 1 d d 1 d 1 0100 0101 0 d d 0 0 d 1 d 0101 0110 0 d d 0 1 d d 1 0110 0111 0 d d 0 d 0 1 d 0111 1000 1 d d 1 d 1 d 1 1000 1001 d 0 0 d 0 d 1 d 1001 0010 d 1 0 d 1 d d 1

Karnaugh Map for J0 :

 q3q2 00 01 11 10

q1q0    00                                01                                11                                10

Boolean Expression:

OUTPUT, J0= q3'q1q0' + q3' q2q0' + q3q2'q1'q0'

Karnaugh Map for K0 :

 q3q2 00 01 11 10

q1q0            00                                           01                                           11                                           10

 x x 1 d d 1 1 d x x x x d 1 x x

Boolean Expression:

OUTPUT, J0= q3'q1q0 + q3' q2 + q3q2'q1'q0

b)     Simulation: (Opportunity of Distinction)

Output

OUTPUT TRUTH TABLE: (Opportunity of Merit)

 INPUTS OUTPUT A B C D COUNT VALUE 0 0 1 0 2 0 0 1 1 3 0 1 0 0 4 0 1 0 1 5 0 1 1 0 6 0 1 1 1 7 1 0 0 0 8 1 0 0 1 9 0 0 1 0 2

CIRCUIT OPERATION FOR ASYNCHRONOUS UP COUNTER TO COUNT 0 TO F

Above circuit shows the asynchronous counter to count from 2 to 9. According to requirement initial value is set to 2 and then starts counting. Here it is up counting from 2 to 9. MSB and LSB are connected to a NAND gate. If both inputs are high then based on NAND truth table OUTPUT of NAND gate is LOW.  When 9 comes means MSB and LSB are HIGH then NAND gives OUTPUT LOW. As this OUTPUT terminal is connected to clear line of 3 FFs except C bit, all are these 3 are cleared and bit C is connected via NOT gate to the SET of this FF. As a result OUTPUT generated is 0010. Then start again and again.

REFERENCES:

1)      Digital Circuit design by Tocci.

2)      Digital Circuits and Design by S. Salivahanan and S Arivazhagan.

PART  A:

a)      Boolean Expression:

OUTPUT, Y= AB'(C      D) = AB'(C EXOR  D)  =AB'C'D + AB'CD'

b)     Boolean Expression in SOP form:

OUTPUT, Y= AB'C'D + AB'CD'

c)      Simulation : (Opportunity of Distinction)

Circuit Diagram:

Output for AB'CD'

Output for AB'C'D

OUTPUT FINAL ONLY:

OUTPUT FOR EACH BIT:

OUTPUT FROM LOGIC ANALYSER:

d)     Truth Table:

 INPUTS OUTPUT A B C D Y 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 1 0 0 0 1 1 1 0 1 0 0 0 0 1 0 0 1 1 1 0 1 0 1 1 0 1 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 0 0 1 1 1 1 0

K-MAP (Opportunity of Merit)

 AB 00 01 11 10

CD   00                                01                                11                                10

 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

Boolean Expression:

OUTPUT, Y= AB'C'D + AB'CD'

e)  CIRCUIT OPERATION: (Opportunity of Distinction)

According to the output expression generated two 4-input AND gates are connected to generate AB'C'D and  AB'CD'.

After that for sum of these two OR gate is used and form a combination of AB'C'D + AB'CD'.

Finally output is shown by logic analyzer, where each inputs and output are shown in one figure but in different line.

In CRO all inputs and output are shown in same line.

REFERENCES:

1) Digital Circuits and Design by S. Salivahanan and S Arivazhagan.

2) Digital Circuit design by Tocci.

PART B:

a) Design a 4-bit asynchronous counter using JK flip -flop to count between 2 and 9:

Flow Diagram:

To design a counter with 8 states, the number of flip-flops required can be found using the equation 2^n>=N >=2^n-1

Where n = number of flip flop required.

N = Number of states present in the counter.

For given condition N = 8 Number of states present in the counter

Thus n = 3 number of flip flop required.

Sequence Table:

 PRESENT STATE (PS) NEXT STATE (NS) q3q2q1q0 Q3Q2Q1Q0 0010 0011 0011 0100 0100 0101 0101 0110 0110 0111 0111 1000 1000 1001 1001 0010

Excitation Table:

 PRESENT STATE (PS) NEXT STATE (NS) Excitation Inputs q3q2q1q0 Q3Q2Q1Q0 J3 K3 J2 K2 J1 K1 J0 K0 0010 0011 0 d 0 d d 0 1 d 0011 0100 0 d 1 d d 1 d 1 0100 0101 0 d d 0 0 d 1 d 0101 0110 0 d d 0 1 d d 1 0110 0111 0 d d 0 d 0 1 d 0111 1000 1 d d 1 d 1 d 1 1000 1001 d 0 0 d 0 d 1 d 1001 0010 d 1 0 d 1 d d 1

Karnaugh Map for J0 :

 q3q2 00 01 11 10

q1q0    00                                01                                11                                10

 x x d 1 1 d d 1 x x x x 1 d x x

Boolean Expression:

OUTPUT, J0= q3'q1q0' + q3' q2q0' + q3q2'q1'q0'

Karnaugh Map for K0 :

 q3q2 00 01 11 10

q1q0            00                                           01                                           11                                           10

 x x 1 d d 1 1 d x x x x d 1 x x

Boolean Expression:

OUTPUT, K0= q3'q1q0 + q3' q2 + q3q2'q1'q0

b)     Simulation: (Opportunity of Distinction)

Step 1: Design basic asynchronous UP counter to count 0 to F

Output:

Step2: Then design for upto 9

Place a NAND gate having 2 inputs. When combination "9" comes it generates Zero output.

Step 3: then connect to that output to clear line. That means it will clear output when 9 comes and start from initial value.

Step 4: Use a NOT gate to generate high signal to set D1 bit high for initial value "2"

OUTPUT TRUTH TABLE: (Opportunity of Merit)

 INPUTS OUTPUT A B C D COUNT VALUE 0 0 1 0 2 0 0 1 1 3 0 1 0 0 4 0 1 0 1 5 0 1 1 0 6 0 1 1 1 7 1 0 0 0 8 1 0 0 1 9 0 0 1 0 2

CIRCUIT OPERATION FOR ASYNCHRONOUS UP COUNTER TO COUNT 0 TO F

Above circuit shows the asynchronous counter to count from 2 to 9. According to requirement initial value is set to 2 and then starts counting. Here it is up counting from 2 to 9. MSB and LSB are connected to a NAND gate. If both inputs are high then based on NAND truth table OUTPUT of NAND gate is LOW.  When 9 comes means MSB and LSB are HIGH then NAND gives OUTPUT LOW. As this OUTPUT terminal is connected to clear line of 3 FFs except C bit, all are these 3 are cleared and bit C is connected via NOT gate to the SET of this FF. As a result OUTPUT generated is 0010. Then start again and again.

REFERENCES:

1)      Digital Circuit design by Tocci.

2)      Digital Circuits and Design by S. Salivahanan and S Arivazhagan.