Programme: HND Electronic Engineering

Unit Number and Name: Unit 117 Digital and Analogue Devices and Circuits F/602/2237

Level: QCF Level 5

Assignment Title - Digital Electronic Circuits

AIM OF THIS ASSIGNMENT

You will undertake a number of investigative and practical activities designed to develop your understanding of digital electronic circuits.

ASSIGNMENT OBJECTIVES:

In this assignment, you will need to show that you can design, build and test digital electronic circuits.

1. Compare different digital electronic device families.

2. Design and construct combinational and sequential digital electronic circuits using logic devices.

3. Test digital electronic circuits.

 Merit Descriptors                            In order to achieve a Merit the learner must: Indicative Characteristics           The learners evidence shows: Contextualised Evidence.           To achieve the grade you will need to. M1 - Identify and apply strategies to find appropriate solutions. Complex problems with more than one variable have been explored. Design a sequential circuit using external inputs. M2 - Select/design and apply appropriate methods/techniques. A range of methods and techniques have been applied. Design a sequential logic circuit using an alternative model.
 Distinction Descriptors              In order to achieve a Distinction the learner must: Indicative Characteristics          The learners evidence shows: Contextualised Evidence.         To achieve the grade you will need to. D2 - Take responsibility for managing and organizing activities. Autonomy/independence had been demonstrated. Demonstrate that you have completed a complete task on your own, without any support. D3 - Demonstrate convergent/lateral/creative thinking Problems have been solved Add additional inputs and solve a higher level problem

You have completed your engineering apprenticeship and have a position in the design department of your company. You have been asked by your line manager to analyse logic families and to produce combinational and sequential logic circuits.

a) Using Manufacturer's datasheets complete a table using Nominal values for the following logic families: LS TTL, ALS TTL, CMOS, HCMOS, (Include excerpts from datasheet in appendix)

b) Briefly explain the different types of scales of integration: SSI, MSI, LSI, VLSI. (one sentence each)

c) Briefly explain the different types of programmable devices: PROM, PAL, PLA. (one-two sentances)

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You are to design a 3-bit counter with outputs Q0, Q1, Q2, where Q0 is the least significant bit.

The sequence 0, 2, 3, 5, 7, 6, 4, 0, 2 . . . is generated:

010 (2)

011 (3)

101 (5)

111 (7)

110 (6)

100 (4)

000 (0)

Part 1 - Design the circuit. (Use any type of flip-flops e.g., JK T or D, and any gates)

Opportunity for merit -

Design the circuit using only another type of flip-flop and NAND gates logic.

Opportunity for merit -

Re-design the circuit with an UP/DOWN counter input, so that the sequence can be reversed. The counter has a single input D, when D is low the counter counts up the sequence, when D is high the counter counts down the sequence.

Use the Moore model (This requires outputs to be decoded)

Part 2 - Using circuit simulation software, draw a circuit diagram from Task 2, Part 1 and simulate its operation.

Demonstrate the circuit operation to your tutor.

Opportunity for Distinction -

Re-design the circuit with an UP/DOWN counter input, so that the sequence can be reversed. The counter has a single input D, when D is low the counter counts up the sequence, when D is high the counter counts down the sequence.

Use the Mealy model.

Your answer should include truth tables, Karnaugh maps and be made using only JK type flips flops. Demonstrate to your tutor that the circuit works using simulation software.

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Design a circuit using only NAND gates, whose output goes HIGH when its inputs are: A is high and B is low and either input C or input D is also HIGH and make a sketch. Derive a Boolean equation that describes the performance of the required circuit.

Part 2 - a) Using a 'Logic Tutor' design and construct the circuit using the output connected to a LED or Logic-probe, and produce a four-variable truth table and apply all combinations of input variables to the circuit and each time note the logical state of the output.

b) Demonstrate and test the circuit operation for your tutor.

Opportunity for distinction -

You need to demonstrate that you have completed the assignment without support from your lecturer or peers.

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#### Are You Looking for Compare different digital electronic device families?

Part 1:

(i) Opportunity for merit

Problem: Design the counter with another type of flip flop and NAND gates only (M2)

Solution:  Here D-flip-flops are used to design the given counter with synchronous clock input.

Sequence: 0-2-3-5-7-6-4-0-2- .................

Design procedure:

step 1: construction of finite state machine

since there is no external input considered here, It is default that the state transitions occur at the occurrence of a clock pulse.

Step 2: Transition table

 Q2 Q1 Q0 Q2+ Q1+ Q0+ D2 D1 D0 0 0 0 0 0 1 0 1 0 0 0 1 X X X X X X 0 1 0 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1 1 0 0 0 0 0 0 0 0 1 0 1 1 1 1 1 1 1 1 1 0 1 0 0 1 0 0 1 1 1 1 1 0 1 1 0

Note: the transition table for d flip flop is

STEP3: k-map

D2:     Q1Q0

00 01 11  10

 0 X 1 0 0 1 1 1

Q2    0

1

D2=Q2Q0+ Q1Q0+Q2Q1

D1:     Q1Q0

Q2            00  01  11  10

 1 X 0 1 0 1 1 0

0

1

D1= Q2Q0 + Q2'Q0'

D0:    Q1Q0

Q2      00   01   11  10

 0 X 1 1 0 1 0 0

0

1

D0= Q1'Q0 + Q2'Q1

Step4:  circuit construction using NAND gates

To construct the circuit using nand gates consider the double complement of the expressions.

We get,

(D2')'=  [(Q2Q0)' . (Q1Q0)' .  (Q2Q1)']'

(D1')'=  [(Q2Q0)' . (Q2'Q0')']'

(D0')'=  [(Q1'Q0)' . (Q2'Q1)']'

STEP5: complete circuit

(ii) Opportunity for merit

Problem : re-design the circuit with up/down counter using ' MOORE MODEL' , so that the sequence can be reversed. (M 1)

ie., if  input D=0, upcount ( 0-2-3-5-7-6-4-)

if input D =1, downcount( 4-6-7-5-3-2-0) reverse direction

Solution:

In moore machine model, the output of the combinational circuit depend only on the present input, which is D.

In the state diagram each state is represented by characteristic output produced when the FSM is in that state.

Transition Table:

 Q2 Q1 Q0 D Q2+ Q1+ Q0+ D2 D1 D0 0 0 0 0 0 0 1 0 0 1 0 0 1 0 X X X X X X 0 1 0 0 0 1 1 0 1 1 0 1 1 0 1 0 1 1 0 1 1 0 0 0 0 0 0 0 0 0 1 0 1 0 1 1 1 1 1 1 1 1 0 0 1 0 0 1 0 0 1 1 1 0 1 1 0 1 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 1 X X X X X X 0 1 0 1 0 0 0 0 0 0 0 1 1 1 0 1 0 0 1 0 1 0 0 1 1 1 0 1 1 0 1 0 1 1 0 1 1 0 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 0 1

K- MAP:

Implementation:  The circuit implementation is done in the tool Lt_spice using built=in components,which gives accurate transient analysis for the circuit. The gate used is 6-input nandgate , here only 2 inputs are used and the others are left floating which doesn't affect the output.

Part 2: opportunity for distinction

problem : re-design the up/down counter in part 1 using ' MEALY MODEL' using JK flip-flops.

Solution:

In mealy machine, the output of the FSM depends on both the present state and the present input. Hence the states are represented by a notation and the outputs and the inputs are represented on the transition from one state to another.

Here JK flip flops are used.

State diagram: dotted line shows that input is 1 and thick line shows that input is 0. States are not shown with fixed  output values as in moore machine.

JK excitation table:

Transition table for the up/down counter:

 Q2 Q1 Q0 D Q2+ Q1+ Q0+ J2 K2 J1 K1 J0 K0 0 0 0 0 0 0 1 0 X 0 X 1 X 0 0 1 0 X X X X X X X X X 0 1 0 0 0 1 1 0 X X 0 1 X 0 1 1 0 1 0 1 1 X X 1 X 0 1 0 0 0 0 0 0 X 1 0 X 0 X 1 0 1 0 1 1 1 X 0 1 X X 0 1 1 0 0 1 0 0 X 0 X 1 0 X 1 1 1 0 1 1 0 X 0 X 0 X 1 0 0 0 1 1 0 0 1 X 0 X 0 X 0 0 1 1 X X X X X X X X X 0 1 0 1 0 0 0 0 X X 1 0 X 0 1 1 1 0 1 0 0 X X 0 X 1 1 0 0 1 1 1 0 X 0 1 X 0 X 1 0 1 1 0 1 1 X 1 1 X X 0 1 1 0 1 1 1 1 X 0 X 0 1 X 1 1 1 1 1 0 1 X 0 X 1 X 0

K-Maps:

Circuit implementation:

Note : In Lt-spice the built in and/nand component is used. But for the implementation only AND gate is used.